Hybrid nanostructure scheme and methods for forming the same

A transistor, comprising:

• a gate structure wrapping around a plurality of nanostructures disposed over a substrate;
• an undoped semiconductor layer in and over the substrate, wherein a top surface of the undoped semiconductor layer is coplanar with or above a top surface of a bottommost nanostructure of the plurality of nanostructures;
• a dielectric layer disposed between the undoped semiconductor layer and the bottommost nanostructure of the plurality of nanostructures;
• and
• a source/drain feature adjacent to the plurality of nanostructures, wherein a bottom surface of the source/drain feature is in direct contact with a top surface of the undoped semiconductor layer.

A method, comprising:

• forming a first fin-shaped active region extending from a substrate and comprising a plurality of channel layers interleaved by a plurality of sacrificial layers;
• forming a first gate stack over a first channel region of the first fin-shaped active region;
• recessing a first source/drain region of the first fin-shaped active region to form a first source/drain opening;
• forming a first semiconductor layer in a bottom portion of the first source/drain opening;
• forming a first dielectric layer extending along a sidewall surface of a middle portion of the first source/drain opening and on the first semiconductor layer, wherein an entirety of a sidewall surface of a bottommost channel layer of the plurality of channel layers is covered by the first dielectric layer;
• forming a second semiconductor layer on the first semiconductor layer, wherein a sidewall surface of the second semiconductor layer is in direct contact with the first dielectric layer;
• forming a first source/drain feature on the second semiconductor layer;
• and
• replacing the first gate stack and the plurality of sacrificial layers with a gate structure.