Integrated circuit structures having dual stress gates

An integrated circuit structure, comprising:

• a first vertical stack of horizontal nanowires;
• a second vertical stack of nanowires laterally spaced apart from the first vertical stack of horizontal nanowires.
• an NMOS gate electrode over the first vertical stack of horizontal nanowires, the NMOS gate electrode having a tensile layer extending from a top to a bottom of the first vertical stack of horizontal nanowires;
• and
• a PMOS gate electrode separated from the NMOS gate electrode by a dielectric cut plug structure, the PMOS gate electrode over the second vertical stack of horizontal nanowires, the PMOS gate electrode having a compressive layer extending from a top to a bottom of the second vertical stack of horizontal nanowires, wherein the tensile layer of the NMOS gate electrode is not included in the PMOS gate electrode.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a first vertical stack of horizontal nanowires;
• a second vertical stack of nanowires laterally spaced apart from the first vertical stack of horizontal nanowires.
• an NMOS gate electrode over the first vertical stack of horizontal nanowires, the NMOS gate electrode having a tensile layer extending from a top to a bottom of the first vertical stack of horizontal nanowires;
• and
• a PMOS gate electrode having a side in contact with a side of the NMOS gate electrode to provide a PN junction or the PMOS gate electrode separated from the NMOS gate electrode by a dielectric cut plug structure, the PMOS gate electrode over the second vertical stack of horizontal nanowires, and the PMOS gate electrode having a compressive layer extending from a top to a bottom of the second vertical stack of horizontal nanowires, wherein the tensile layer of the NMOS gate electrode is not included in the PMOS gate electrode.