Gallium nitride enhancement mode device
AssigneeAnalog Devices, Inc.
InventorsJames G. Fiorenza, Puneet Srivastava, Daniel Piedra
Life of this patent
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Abstract
An enhancement mode compound semiconductor field-effect transistor (FET) includes a source, a drain, and a gate located therebetween. The transistor further includes a first gallium nitride-based hetero-interface located under the gate and a buried region, located under the first hetero-interface, the buried p-type region configured to determine an enhancement mode FET turn-on threshold voltage to permit current flow between the source and the drain.
Claims21
(canceled)
A method of manufacturing a semiconductor device, the method comprising:
- forming a layer of deactivated p-type material over a substrate;
- forming a layer of a first compound semiconductor material over the layer of deactivated p-type material;
- forming a channel layer having a hetero-structure by forming a layer of a second compound semiconductor material over the layer of the first compound semiconductor material;
- forming a recess in the channel layer and the layer of deactivated p-type material;
- and
- forming an activated p-type region adjacent the recess in the layer of deactivated p-type material by annealing the semiconductor device while leaving a deactivated p-type region.
A semiconductor device comprising:
- a substrate;
- a layer of deactivated p-type material disposed over the substrate;
- a layer of a first compound semiconductor material disposed over the layer of deactivated p-type material;
- a channel layer having a hetero-structure comprising a layer of a second compound semiconductor material disposed over the layer of the first compound semiconductor material;
- a recess formed in the channel layer and the layer of deactivated p-type material;
- an activated p-type region formed in the layer of deactivated p-type material and adjacent the recess;
- a deactivated p-type region formed adjacent to the activated p-type region;
- a source electrode formed in the recess;
- and
- a gate electrode formed over the activated p-type region and adjacent the source electrode.
A semiconductor device comprising:
- a substrate;
- a layer of deactivated p-type material disposed over the substrate;
- a layer of a first compound semiconductor material disposed over the layer of deactivated p-type material;
- a channel layer having a hetero-structure comprising a layer of a second compound semiconductor material disposed over the layer of the first compound semiconductor material;
- a first recess formed in the channel layer and the layer of deactivated p-type material;
- a second recess formed in the channel layer;
- an activated p-type region formed in the layer of deactivated p-type material and adjacent the first recess;
- a deactivated p-type region formed adjacent to the activated p-type region;
- a source electrode formed in the first recess;
- and
- a gate electrode formed over the activated p-type region and adjacent the source electrode, wherein the gate electrode is formed within the second recess.
Dependencies are inferred from the claim text.