Semiconductor memory cell structure including a hydrogen absorption layer

A semiconductor device, comprising:

• a plurality of back end dielectric layers;
• and
• a memory cell structure, in the plurality of back end dielectric layers, comprising:
• a transistor structure;
• and
• a capacitor structure, above the transistor structure, comprising:
• a bottom electrode layer;
• a dielectric layer over the bottom electrode layer;
• a first top electrode layer over the dielectric layer;
• a second top electrode layer over the first top electrode layer;
• and
• a hydrogen absorption layer between the first top electrode layer and the second top electrode layer.

A method, comprising:

• forming a gate structure of a transistor structure included in a memory cell structure of a semiconductor device;
• forming a gate dielectric layer of the transistor structure over the gate structure;
• forming a channel layer of the transistor structure on the gate dielectric layer;
• forming a plurality of source/drain regions of the transistor structure on the channel layer;
• forming a source/drain interconnect structure of the memory cell structure on a source/drain region of the plurality of source/drain regions;
• forming a bottom electrode, of a capacitor structure included in the memory cell structure, on the source/drain interconnect structure;
• forming a hydrogen absorption layer of the capacitor structure over the bottom electrode;
• and
• forming a top electrode of the capacitor structure over the hydrogen absorption layer.