US 2025/0098182 A1 · 3D MEMORY DEVICES AND STRUCTURES WITH MEMORY ARRAYS AND METAL LAYERS

Abstract

A semiconductor device including: a first level including at least four independently controlled first memory arrays, where the first level includes first transistors; a second level disposed on top of the first level, where the second level includes second memory arrays; and a third level disposed on top of the second level, where the third level includes third transistors, at least one metal layer, and third memory arrays; a fourth level disposed on top of the third level, where the fourth level includes fourth transistors, another at least one metal layer, and is bonded to the third level, where the bonded includes metal-to-metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes; and a via connection through the second level and the third level, and where the fourth level includes at least one SRAM memory array.

Claims20

Dependent claims

A semiconductor device, the device comprising:

a first level comprising at least four independently controlled first memory arrays,
wherein said first level comprises a plurality of first transistors;
a second level disposed on top of said first level,
wherein said second level comprises a plurality of second memory arrays;
a third level disposed on top of said second level,
wherein said third level comprises a plurality of third transistors and at least one metal layer,
wherein said third level comprises a plurality of third memory arrays;
a fourth level disposed on top of said third level,
wherein said fourth level comprises a plurality of fourth transistors and another at least one metal layer,
wherein said fourth level is bonded to said third level,
wherein said bonded comprises a plurality of metal-to-metal bonding regions,
wherein said first level comprises first filled holes,
wherein said second level comprises second filled holes;
and
a via connection through said second level and said third level,
wherein said fourth level comprises at least one SRAM memory array.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/963,630Filed 28 Nov 2024

Priority

10 Oct 2016

Published

20 Mar 2025

Term ends

Not estimatedThe source records don’t support an estimate.

Classification51 codes

G11C 11/005
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor: comprising combined but…
H10B 80/00
Assemblies of multiple devices comprising at least one memory device covered by
G11C 11/5628
Using charge storage in a floating gate: programming or writing circuits; Data input circuits
G11C 11/5635
Programming or writing circuits; Data input circuits: erasing circuits

Family

Application62/406,376Us provisional application · filed 10 Oct 2016

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