Process technique for embedded memory

A method for manufacturing an integrated circuit comprising:

• defining a memory region and a non-memory region on a semiconductor wafer;
• depositing a first interlayer dielectric layer on a first bottom metal layer in the memory region and a second bottom metal layer in the non-memory region;
• forming a first conductive structure in the memory region and a second conductive structure in the non-memory region by etching the first interlayer dielectric layer using a first photolithography process comprising a first photomask, wherein the first conductive structure is configured to be a first bottom electrode in the memory region;
• depositing a memory stack layer in the memory region and the non-memory region;
• forming a memory element in the memory region by etching the memory stack layer using a second photolithography process comprising a second photomask;
• depositing a second interlayer dielectric layer in the memory region and the non-memory region;
• and
• forming a first via in the memory region and a second via in the non-memory region by etching the second interlayer dielectric layer using a third photolithography process comprising a third photomask, wherein the first photomask and the third photomask comprise a same pattern.