Hierarchical memory architecture including on-chip multi-bank non-volatile memory with low leakage and low latency

A structure comprising:

• well regions within a semiconductor substrate;
• an insulator layer on the semiconductor substrate over the well regions;
• memory banks, wherein each memory bank includes a corresponding well region and an array of non-volatile memory cells including transistors on the insulator layer above the corresponding well region;
• and
• a bias control circuit connected to the well regions,
• wherein the bias control circuit outputs back biasing voltages for the memory banks to the well regions and independently switches the back biasing voltages between a reverse back biasing voltage and a forward back biasing voltage based on addresses in access requests and further based on results of cache data retrieval processes performed in response to the access requests.

A structure comprising:

• well regions within a semiconductor substrate;
• an insulator layer on the semiconductor substrate over the well regions;
• memory banks, wherein each memory bank includes a corresponding well region and an array of non-volatile memory cells including transistors on the insulator layer above the corresponding well region;
• a bias control circuit including:
• bias voltage selectors for the memory banks connected to the well regions, respectively;
• and
• logic blocks for the memory banks connected to the bias voltage selectors, respectively, and
• a cache controller connected to the logic blocks,
• wherein the bias voltage selectors output back biasing voltages for the memory banks to the well regions, and
• wherein the logic blocks cause the bias voltage selectors to independently switch the back biasing voltages between a reverse back biasing voltage and a forward back biasing voltage based on addresses in access requests and further in response to inputs received from the cache controller indicating results of cache data retrieval processes performed in response to the access requests.