Semiconductor memory device and method of manufacturing the same

A method of manufacturing a semiconductor memory device, the method comprising:

• forming a memory cell array on a substrate so that the memory cell array includes a gate stack including interlayer insulating layers and conductive patterns alternately stacked in a vertical direction, a core insulating layer passing through the gate stack and having an end extending into the substrate, a channel layer surrounding a sidewall and the end of the core insulating layer, and a memory layer extending from a region between the channel layer and the gate stack to a region between an end of the channel layer and the substrate;
• removing the substrate to expose the memory layer;
• exposing the core insulating layer by etching the exposed memory layer and the channel layer;
• forming a first source layer and a buffer layer on an entire structure including the core insulating layer, and then performing a planarization process so that an uppermost surface becomes uniform;
• forming a junction region by performing an ion implantation process on an upper end of the channel layer;
• and
• performing a heat treatment process on the first source layer and the junction region after removing the buffer layer.

A method of manufacturing a semiconductor memory device, the method comprising:

• forming a memory cell array on a substrate so that the memory cell array includes a gate stack including insulating layers and conductive layers alternately stacked, a core insulating layer penetratings the gate stack and having an end extending into the substrate, a channel layer surrounding a sidewall and the end of the core insulating layer, and a memory layer extending from a region between the channel layer and the gate stack to a region between an end of the channel layer and the substrate;
• removing the substrate to expose the memory layer;
• exposing the core insulating layer by etching the exposed memory layer and the channel layer, and forming an opening between an upper end of the memory layer and an upper end of the core insulating layer by etching the exposed memory layer and the channel layer so that an upper surface height of the channel layer is lower than an upper surface height of the gate stack;
• and
• forming a first source layer to surround the upper surface of the gate stack and a protrusion of the core insulating layer and to fill the opening.