Ultra-thin body array transistor for 4f2

A vertical cell array transistor (VCAT), comprising:

• a plurality of bit lines arranged in a first horizontal direction;
• a plurality of word lines arranged in a second horizontal direction;
• a plurality of channels extending in a vertical direction that is generally orthogonal to the first horizontal direction and the second horizontal direction such that the plurality of word lines intersect with a gate region of the plurality of channels;
• wherein the plurality of channels each have a first source/drain region at a first end, a second source/drain region at a second end, and a channel body disposed between the first end and the second end, wherein the channel body has a thickness that is greater than or about 5% less than a thickness of at least a portion of the first source/drain region and the second source/drain region.

A method of forming a vertical cell array transistor (VCAT), comprising:

• etching a substrate to form one or more shallow trench isolations and a plurality of vertically extending channels;
• depositing a first protective dielectric material in the shallow trench isolation adjacent to a first source/drain region at a first end of the vertically extending channel;
• depositing a sacrificial dielectric material over the first protective dielectric material;
• depositing a second protective dielectric material over the sacrificial dielectric material adjacent to a second source/drain region at a second end of the vertically extending channel;
• removing the sacrificial dielectric material;
• and
• reducing a thickness of a channel body of the one or more of the vertically extending channels, wherein the channel body is disposed between the first source/drain region and the second source/drain region.