Semiconductor memory device

A semiconductor memory device, comprising:

• a laminated structure with a plurality of first layers and a plurality of second layers alternately stacked in a first direction;
• a common electrode that extends through the laminated structure in the first direction and extends a second direction crossing the first direction to divide the laminated structure into a first side and second side, the common electrode being between the first side and the second side in a third direction crossing the first and second directions;
• a first bit line in a first section on the first side of the laminated structure, the first bit line extending in the first direction through the laminated structure;
• and
• a second bit line in a second section on the first side of the laminated structure, the second bit line extending in the first direction through the laminated structure, the second bit line being spaced from the first bit line in the second direction, wherein
• each first layer includes:
• a word line that extends in the second direction,
• a first semiconductor layer that extends in the second direction alongside word line and is connected to the first bit line,
• a second semiconductor layer that extends in the second direction alongside the word line, the second semiconductor layer being spaced from the first semiconductor layer in the second direction and connected to the second bit line,
• a first gate insulating layer between the word line and the first semiconductor layer,
• a second gate insulating layer between the word line and the second semiconductor layer,
• a first part of a first capacitor connected to the first semiconductor layer;
• and
• each second layer includes:
• an insulating layer which has a part between word lines adjacent to each other in the first direction, a part between first semiconductor layers adjacent to each other in the first direction, and
• a second part of the first capacitor that is in an adjacent first layer.