US 2025/0098142 A1 · DOUBLE CHANNEL SINGLE INNER GATE THREE-DIMENSIONAL (3D) DYNAMIC RANDOM-ACCESS MEMORY (DRAM) DEVICES

Abstract

A memory cell array includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including a cell transistor having a source region electrically connected to a bit line extending in the first direction, a drain region, a word line layer, a lower channel layer electrically connected to the source region and the drain region and disposed below the word line layer in the first direction, and an upper channel layer electrically connected to the source region and the drain region and disposed above the word line layer in the first direction, and a cell capacitor electrically connected to the drain region, and a plurality of inter-level isolation layers, each separating adjacent memory levels of the plurality of memory levels.

Claims20

Dependent claims

A memory cell array, comprising:

a plurality of memory levels stacked in a first direction, each of the plurality of memory levels comprising:
a cell transistor having:
a source region electrically connected to a bit line extending in the first direction;
a drain region;
a word line layer;
a lower channel layer electrically connected to the source region and the drain region and disposed below the word line layer in the first direction;
and
an upper channel layer electrically connected to the source region and the drain region and disposed above the word line layer in the first direction;
and
a cell capacitor electrically connected to the drain region;
and
a plurality of inter-level isolation layers, each separating adjacent memory levels of the plurality of memory levels.

9 more elements

A method of forming cell transistors in a semiconductor memory device, comprising:

forming a transistor slit through a stacking mold in a first direction, the transistor slit extending in a second direction that is orthogonal to the first direction, the stacking mold comprising a plurality of unit stacks, each unit stack comprising:
a lower sacrificial layer,
a lower channel layer over the lower sacrificial layer,
an upper sacrificial layer on the lower channel layer, and
an upper channel layer on the upper sacrificial layer stacked in the first direction;
performing a recess forming process, to form recesses in the upper sacrificial layers from sidewalls of the transistor slit;
forming a first insulator layer on exposed surfaces of the lower channel layers and the upper channel layers within the transistor slit and the recesses;
filling the transistor slit and the recesses with a first nitride layer;
performing a deep trench isolation (DTI) lateral cut process, to form DTI gaps through the stacking mold in the first direction, the DTI gaps extending in a third direction that is orthogonal to the first and second directions;
filling the DTI gaps with a second insulator layer;
selectively removing the first nitride layer from the transistor slit and the recesses;
forming word line (WL) slits each between the lower channel layer and the upper channel layer between adjacent unit stacks of the stacking mold;
performing a WL slit fill process, to fill the WL slits and the recesses with a second nitride layer;
selectively removing the second insulator layer;
selectively removing the lower sacrificial layer and forming inter-level isolation gaps each between the lower channel layer and the upper channel layer between adjacent unit stacks of the stacking mold;
filling the inter-level isolation gaps with inter-level isolation layers;
performing a gate oxide formation process, to form a gate oxide layer on exposed inner surfaces of the WL slit and the recesses;
and
performing a WL slit fill process, to fill the WL slits with a word line layer.

16 more elements

Dependencies are inferred from the claim text.

Double channel single inner gate three-dimensional (3d) dynamic random-access memory (dram) devices

Life of this patent

Double channel single inner gate three-dimensional (3d) dynamic random-access memory (dram) devices

Life of this patent

Abstract

Claims20