US 2025/0098141 A1Published application

Semiconductor memory device

AssigneeKioxia Corporation

InventorMutsumi OKAJIMA

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Abstract

A semiconductor memory device includes: a substrate; a first wiring; a first semiconductor layer disposed between the substrate and the first wiring; second semiconductor layers disposed between the first semiconductor layer and the first wiring; a first via-wiring connected to the first and the second semiconductor layers; a first memory portion connected to the first semiconductor layer; a first gate electrode opposed to the first semiconductor layer; a second wiring connected to the first gate electrode; connection electrodes connected to the second semiconductor layers; second gate electrodes opposed to the second semiconductor layers; third wirings disposed between the second and the first wiring and connected to the second gate electrodes; a fourth wiring connected to the first memory portion; a fifth wiring connected to the connection electrodes in common; and an insulating layer disposed between the fourth wiring and the fifth wiring.

Claims20

Dependent claims

A semiconductor memory device comprising:

a substrate;
a first wiring disposed on one side in a first direction intersecting with a surface of the substrate with respect to the substrate and extending in a second direction intersecting with the first direction;
a first semiconductor layer disposed between the substrate and the first wiring;
a plurality of second semiconductor layers disposed between the first semiconductor layer and the first wiring and stacked in the first direction;
a first via-wiring extending in the first direction and electrically connected to the first semiconductor layer and the plurality of second semiconductor layers;
a first memory portion electrically connected to the first semiconductor layer;
a first gate electrode opposed to the first semiconductor layer;
a second wiring extending in a third direction intersecting with the first direction and the second direction and electrically connected to the first gate electrode;
a plurality of connection electrodes disposed between the first memory portion and the first wiring, stacked in the first direction, and electrically connected to the respective plurality of second semiconductor layers;
a plurality of second gate electrodes disposed between the first gate electrode and the first wiring, stacked in the first direction, and opposed to the respective plurality of second semiconductor layers;
a plurality of third wirings disposed between the second wiring and the first wiring, stacked in the first direction, extending in the third direction, and electrically connected to the respective plurality of second gate electrodes;
a fourth wiring extending in the first direction and electrically connected to the first memory portion;
a fifth wiring extending in the first direction and electrically connected to the plurality of connection electrodes in common;
and
an insulating layer disposed between the fourth wiring and the fifth wiring.

12 more elements

A semiconductor memory device comprising:

a plurality of first semiconductor layers stacked in a first direction;
a first wiring disposed on one side in the first direction of the plurality of first semiconductor layers, the first wiring extending in a second direction intersecting with the first direction;
a plurality of second semiconductor layers disposed between the plurality of first semiconductor layers and the first wiring and stacked in the first direction;
a first via-wiring extending in the first direction and electrically connected to the plurality of first semiconductor layers and the plurality of second semiconductor layers;
a plurality of first memory portions stacked in the first direction and electrically connected to the respective plurality of first semiconductor layers;
a plurality of first gate electrodes stacked in the first direction and opposed to the respective plurality of first semiconductor layers;
a plurality of second wirings stacked in the first direction, extending in a third direction intersecting with the first direction and the second direction, and electrically connected to the respective plurality of first gate electrodes;
a plurality of connection electrodes disposed between the plurality of first memory portions and the first wiring, stacked in the first direction, and electrically connected to the respective plurality of second semiconductor layers;
a plurality of second gate electrodes disposed between the plurality of first gate electrodes and the first wiring, stacked in the first direction, and opposed to the respective plurality of second semiconductor layers;
a plurality of third wirings disposed between the plurality of second wirings and the first wiring, stacked in the first direction, extending in the third direction, and electrically connected to the respective plurality of second gate electrodes;
a fourth wiring extending in the first direction and electrically connected to the plurality of first memory portions in common;
and
a fifth wiring extending in the first direction and electrically connected to the plurality of connection electrodes in common.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/595,199Filed 4 Mar 2024
Priority: JP 2023-15397220 Sep 2023
Published: 20 Mar 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10B 12/30
Dynamic random access memory [DRAM] devices: dRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
H10B 12/03
For one transistor one-capacitor [1T-1C] memory cells: making the capacitor or connections thereto
H10B 12/05
For one transistor one-capacitor [1T-1C] memory cells: making the transistor
H10B 43/10
EEPROM devices comprising charge-trapping gate insulators: characterised by the top-view layout

Family

No related US applications are recorded in the indexed filing history.

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