Capacitorless 3d dram device and manufacturing method thereof

A capacitorless 3D DRAM device comprising:

• a write bit line extending in a vertical direction;
• a write word line extending in a horizontal direction;
• a write transistor connected to the write bit line and the write word line, and defined to include a first channel material layer, a first gate insulating layer, and a portion of the write word line;
• a read bit line extending in the vertical direction;
• a read word line extending in the horizontal direction;
• and
• a read transistor connected to the read bit line and the read word line, and defined to include a second channel layer pattern including a first portion which is disposed to be adjacent to the read bit line and extends in a horizontal direction, and a second portion which is spaced apart from the read bit line and extends in a direction having a given angle with respect to the first portion, and a second gate insulating layer.

A manufacturing method of capacitorless 3D DRAM comprising:

• forming a stack having a stacked structure including a separation layer, and a first channel material layer, a first gate insulating layer, a first insulating layer, a second insulating layer, and a buffer layer which are sequentially stacked on the separation layer;
• forming a patterned stack including a plurality of pattern portions and first and second pattern extension portions extending in a direction connecting the plurality of pattern portions by patterning the stack, wherein the plurality of pattern portions extend in a first direction, and are spaced apart from each other in a second direction orthogonal to the first direction, and the first and second pattern extension portions extend in the second direction;
• a first structure including the patterned stack and a first filling material by filling the first filling material between the plurality of pattern portions and between the first and second pattern extension portions;
• forming a first vertical hole penetrating through each of the plurality of pattern portions in a vertical direction in the first structure;
• forming a first horizontal hole by removing the first insulating layer from the first pattern extension portion while forming a first recess by recessing the first insulating layer around the first vertical hole of the first structure;
• defining a write transistor including the first channel material layer, the first gate insulating layer, and a portion of a write word line by forming the write word line extending in a horizontal direction in the first recess and the first horizontal hole;
• removing the first filling material from the first structure and removing a portion of the first channel material layer from the first and second pattern extension portions;
• forming a second structure including the plurality of pattern portions, the first and second pattern extension portions, and a second filling material by filling the second filling material between the plurality of pattern portions where the write transistor is defined, and between the first and second pattern extension portions;
• forming a write bit line extending in a vertical direction at a position corresponding to the first vertical hole;
• forming a second vertical hole penetrating through each of the plurality of pattern portions in a vertical direction in the second structure;
• forming a second horizontal hole by removing the second insulating layer from the second pattern extension portion while forming a second recess by recessing the second insulating layer around the second vertical hole of the second structure;
• forming a third recess by recessing the first insulating layer, the first gate insulating layer, and the first channel material layer exposed by the second vertical hole;
• forming a second gate insulating layer on an inner surface of the second vertical hole including surfaces of the second and third recesses, and an inner surface of the second horizontal hole;
• forming a read word line extending in a horizontal direction on the second gate insulating layer in the second recess and the second horizontal hole;
• forming a second channel material layer on the second gate insulating layer and the read word line exposed on the inner surface of the second vertical hole;
• defining a read transistor including a second channel layer pattern and the second gate insulating layer by defining the second channel layer pattern from the second channel material layer;
• and
• forming a read bit line extending in a vertical direction at a position corresponding to the second vertical hole.

A capacitorless 3D DRAM device comprising:

• a write bit line extending in a vertical direction;
• a write word line extending in a horizontal direction;
• a write transistor connected to the write bit line and the write word line, and defined to include a first channel material layer, a first gate insulating layer, and a portion of the write word line;
• a read bit line extending in the vertical direction;
• a read word line extending in the horizontal direction;
• and
• a read transistor connected to the read bit line and the read word line, and defined to include a second channel layer pattern and a second gate insulating layer,
• wherein the write transistor and the read transistor constitute one memory cell, and the write word line and the read word line connected to the one memory cell are arranged at different heights.