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US 2025/0098066 A1Published application
Package comprising a substrate with an interconnect block
AssigneeQUALCOMM Incorporated
InventorsHong Bok WE, Joan Rey Villarba BUOT, Sang-Jae LEE, Zhijie WANG
Life of this patent
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Abstract
A substrate comprising a core layer, at least one first dielectric layer coupled to a first surface of the core layer, at least one second dielectric layer coupled to a second surface of the core layer, a plurality of interconnects located at least partially in the at least one first dielectric layer; a region comprising a plurality of block interconnects of an interconnect block; and a solder resist layer coupled to the at least one first dielectric layer.
Claims21
A substrate comprising:
- a core layer;
- at least one first dielectric layer coupled to a first surface of the core layer;
- at least one second dielectric layer coupled to a second surface of the core layer;
- a plurality of interconnects located at least partially in the at least one first dielectric layer;
- a region comprising a plurality of block interconnects of an interconnect block;
- and
- a solder resist layer coupled to the at least one first dielectric layer.
4 more elements
A package comprising:
- a substrate comprising:
- a core layer;
- at least one first dielectric layer coupled to a first surface of the core layer;
- at least one second dielectric layer coupled to a second surface of the core layer;
- a plurality of interconnects located at least partially in the at least one first dielectric layer;
- a region comprising a plurality of block interconnects of an interconnect block;
- and
- a solder resist layer coupled to the at least one first dielectric layer;
- a first integrated device coupled to the substrate through a first plurality of bump interconnects;
- and
- a second integrated device coupled to the substrate through a second plurality of bump interconnects.
8 more elements
A method for fabricating a substrate, comprising:
- providing a core layer;
- forming at least one first dielectric layer that is coupled to a first surface of the core layer;
- forming at least one second dielectric layer that is coupled to a second surface of the core layer;
- forming a plurality of interconnects located at least partially in the at least one first dielectric layer;
- coupling an interconnect block comprising a plurality of block interconnects, to the at least one first dielectric layer;
- forming an additional first dielectric layer around and over the interconnect block;
- and
- forming a solder resist layer that is coupled to the at least one first dielectric layer.
5 more elements
Dependencies are inferred from the claim text.