Display device

A display device comprising:

• a first electrode;
• a liquid crystal layer on the first electrode;
• a second electrode on the liquid crystal layer;
• a first node electrically connected to the first electrode;
• a second node electrically connected to the second electrode;
• and
• a control circuit, wherein the control circuit includes:
• a first transistor including a base/gate electrode configured to receive a first voltage, a first electrode configured to receive a second voltage, and a second electrode electrically connected to the second node,
• a second transistor including a base/gate electrode configured to receive a third voltage, a first electrode configured to receive the second voltage, and a second electrode electrically connected to the second node;
• and
• a third transistor including a base/gate electrode configured to receive the third voltage, a first electrode electrically connected to the second node, and a second electrode electrically connected to the first node,
• wherein, in a first mode, the control circuit is configured to apply a first node voltage to the first node, and is configured to apply a second node voltage to the second node,
• wherein the second node voltage alternates between a high level voltage higher than a voltage level of the first node voltage and a low level voltage lower than the voltage level of the first node voltage, and
• wherein, in a second mode, the control circuit is configured to short-circuit the first node and the second node.

A display device comprising:

• a first electrode;
• a liquid crystal layer on the first electrode;
• a second electrode on the liquid crystal layer;
• a first node electrically connected to the first electrode;
• a second node electrically connected to the second electrode;
• and
• a control circuit, wherein the control circuit includes:
• a first transistor including a base/gate electrode configured to receive a first voltage, a first electrode configured to receive a second voltage, and a second electrode electrically connected to the second node,
• a second transistor including a base/gate electrode configured to receive a third voltage, a first electrode configured to receive the second voltage, and a second electrode electrically connected to the second node;
• and
• a third transistor including a base/gate electrode configured to receive the third voltage, a first electrode electrically connected to the second node, and a second electrode electrically connected to the first node,
• wherein, in a first mode, the control circuit is configured to apply a first node voltage to the first node, and is configured to apply a second node voltage to the second node,
• wherein the second node voltage alternates between a high level voltage higher than a voltage level of the first node voltage and a low level voltage lower than the voltage level of the first node voltage, and
• wherein, in a second mode, the control circuit is configured to short-circuit the first node and the second node, and
• wherein the first voltage maintains a high level voltage in the first mode and maintains a low level voltage in the second mode.