Semi-custom accelerator device for bootstrappable fully homomorphic encryption

A computing device comprising an FPGA semi-custom accelerator device for hardware acceleration of modular arithmetic operations in a cryptography system, the semi-custom accelerator device including an array of N sets of functional units configured for parallel operation on corresponding ones of N streams of c-bit-width coefficients and producing corresponding ones of N streams of results, comprising:

• an interface to a host CPU configured to execute a fully homomorphic encryption (FHE) application using the FPGA semi-custom accelerator device for bootstrappable FHE (FAB) operations with selection of parameters that are optimized for hardware constraints;
• on-chip memory for storing operands and results, wherein the memory has one or more banks each organized as a two-dimensional arrangement of fixed-size memory units of bit-width m≠c, the two-dimensional arrangement having a width W and depth D of memory units, W being selected to enable storage of an integer number Wm/c of the c-bit-width coefficients across the width of the arrangement, D being selected as a quotient N/(Wm/c) to enable simultaneous retrieval of N coefficients in a single memory access cycle;
• and
• an arithmetic unit coupled to the memory to receive the operands and produce the results, the arithmetic unit including (1) a plurality standard arithmetic blocks configured to operate on corresponding distinct portions of the operands and produce corresponding distinct portions of the results, and (2) custom logic interconnecting the arithmetic blocks in a manner providing for an overall arithmetic operation to produce the results at full-width,
• wherein the array of N sets of functional units efficiently utilizes the memory units of the FPGA on-chip memory and maps data width of the coefficients to that of the memory banks to enable storage of up to a predetermined amount of data on-chip to reduce resource overhead.