Physical coding sublayer with modified bit ordering to improve error burst resiliency

An apparatus comprising:

• a memory;
• and
• one or more integrated circuits configured with digital logic, or a processor device configured with instructions, to perform operations including:
• obtaining a stream of bits received for at least one physical lane from which a plurality of modified logical lanes have been de-multiplexed, which plurality of modified logical lanes is equal in number to a plurality of logical lanes from which an original block of bits was re-ordered according to a mapping that permuted the original block of bits to produce a re-ordered block of bits distributed to the plurality of modified logical lanes that was bit-multiplexed to the at least one physical lane, resulting in the at least one physical lane containing a sequence of a groups of bits for a symbol from one forward error corrected (FEC) codeword followed by a sequence of groups of bits for a symbol from another FEC codeword;
• storing the re-ordered block of bits obtained from the plurality of modified logical lanes to the memory;
• performing an inverse of the mapping on the re-ordered block of bits stored in the memory to obtain the original block of bits;
• and
• distributing the original block of bits to the plurality of logical lanes.

A method performed by a first device that is in communication with a second device, comprising:

• configuring a transmit function to use a modified bit ordering that maps bits from a plurality of logical lanes to a plurality of modified logical lanes that are bit-multiplexed to at least one physical lane for transmission to a second device;
• configuring a receive function to use a modified bit ordering for processing a stream of bits received from the second device on at least one physical lane from which a plurality of modified logical lanes have been de-multiplexed, the plurality of modified logical lanes being equal in number to a plurality of logical lanes from which an original block of bits was re-ordered according to the modified bit ordering;
• receiving an incoming bit stream from the second device;
• attempting to process the incoming bit stream from the second device with the receive function using the modified bit ordering;
• and
• when processing the incoming bit stream using the modified bit ordering is not successful, configuring the receive function of the first device to use an un-modified bit ordering for processing the incoming bit stream from the second device.

An apparatus comprising:

• a memory;
• and
• one or more integrated circuits configured with digital logic, or a processor device configured with instructions, to perform operations by a first device that is in communication with a second device, the operations including:
• configuring a transmit function to use a modified bit ordering that maps bits from a plurality of logical lanes to a plurality of modified logical lanes that are bit-multiplexed to at least one physical lane for transmission to a second device;
• configuring a receive function to use a modified bit ordering for processing a stream of bits received from the second device on at least one physical lane from which a plurality of modified logical lanes have been de-multiplexed, the plurality of modified logical lanes being equal in number to a plurality of logical lanes from which an original block of bits was re-ordered according to the modified bit ordering;
• receiving an incoming bit stream from the second device;
• attempting to process the incoming bit stream from the second device with the receive function using the modified bit ordering;
• and
• when processing the incoming bit stream using the modified bit ordering is not successful, configuring the receive function of the first device to use an un-modified bit ordering for processing the incoming bit stream from the second device.