Recovering scrambling sequence initialization from frozen bits of an uncoded downlink control information vector

A device, comprising:

• one or more memories;
• and
• one or more processors, coupled to the one or more memories, configured to:
• receive a downlink signal from a base station;
• generate a mapping matrix for mapping a scrambling sequence initialization to frozen bits from data of the downlink signal;
• determine an inverse matrix of the mapping matrix;
• obtain, based on the inverse matrix and the frozen bits, a final matrix;
• recover, based on the final matrix, scrambling sequence seed bits;
• and
• perform one or more actions without performing a descrambling operation.

A non-transitory computer-readable medium storing a set of instructions, the set of instructions comprising:

• one or more instructions that, when executed by one or more processors of a device, cause the device to:
• receive a downlink signal from a base station;
• generate a mapping matrix for mapping a scrambling sequence initialization to frozen bits from data of the downlink signal;
• determine an inverse matrix of the mapping matrix;
• obtain, based on the inverse matrix and the frozen bits, a final matrix;
• recover, based on the final matrix, scrambling sequence seed bits;
• and
• perform one or more actions without performing a descrambling operation.