Back to results
US 2025/0096804 A1Published application
Memory device processing
AssigneeLodestar Licensing Group LLC
InventorsTimothy P. Finkbeiner, Troy D. Larsen
Life of this patent
Estimating the term…
Abstract
An example apparatus includes a memory device comprising a plurality of banks of memory cells. A particular bank of memory cells among the plurality of banks includes a system processor resident on a particular bank of the plurality of banks.
Claims20
An apparatus, comprising:
- a system processor coupled with a memory device;
- and
- a plurality of memory banks of the memory device, wherein at least one memory bank of the plurality of memory banks is coupled with a processor, and wherein the system processor is configured to orchestrate execution of processing-in-memory (PIM) instructions via the processor of the at least one memory bank without transferring data via an input/output (I/O) interface of the memory device.
An apparatus, comprising:
- a host;
- a system processor coupled to the host and a memory device;
- and
- the memory device, comprising:
- a plurality of memory banks comprising respective processors, wherein the system processor is configured to orchestrate execution of processing-in-memory (PIM) instructions by the respective processors of the plurality of memory banks without transferring data via an input/output (I/O) interface of the memory device.
2 more elements
An apparatus, comprising:
- a host;
- a system processor coupled to the host;
- and
- a memory device coupled to the system processor, the memory device comprising:
- a plurality of memory banks comprising respective processors, wherein the system processor serves as a supervisory processing device to control operation of the respective processors in association with executing a program without transferring data via an input/output (I/O) interface of the memory device.
2 more elements
Dependencies are inferred from the claim text.