Sample and hold circuit, integrated circuit and method of manufacturing the same

A method of manufacturing an integrated circuit comprising a metal layer, the method comprising:

• providing a plurality of standard cells, each of the plurality of standard cells comprising metal patterns in the metal layer;
• providing a plurality of dummy transistor region cells adjacent to each other and having the metal patterns of the plurality of standard cells;
• and
• removing via connections in the plurality of dummy transistor region cells.

An integrated circuit comprising:

• a transistor region cell comprising a pattern corresponding to a plurality of transistors in a sample and hold circuit;
• and
• a dummy transistor region cell comprising the pattern of the transistor region cell,
• wherein the dummy transistor region cell and the transistor region cell are connected by metal lines provided in a same layer, and
• wherein dummy transistors in the dummy transistor region cell are not connected to the metal lines.