Semiconductor integrated circuit and semiconductor device

A semiconductor integrated circuit generating an L-bit Gray code (where L is an integer larger than or equal to 3) corresponding to a count value of a first clock signal, the semiconductor integrated circuit comprising:

• a first flip-flop including a clock terminal to which the first clock signal is configured to be input, a D terminal, and a Q terminal configured to output a first signal;
• a first terminal to which a selection signal is input;
• a first exclusive NOR circuit configured to
• calculate an exclusive OR of the first signal output from the Q terminal of the first flip-flop and the selection signal, and
• perform inversion calculation on a signal obtained by the calculation of the exclusive OR;
• a second flip-flop including a clock terminal to which the first clock signal is configured to be input, a D terminal to which a signal output from the first exclusive NOR circuit is configured to be input, and a Q terminal;
• a first exclusive OR circuit configured to
• calculate an exclusive OR of a second signal output from the Q terminal of the second flip-flop and the selection signal, and
• output a signal to be input to the D terminal of the first flip-flop;
• a second exclusive NOR circuit configured to
• calculate an exclusive OR of the first signal and the selection signal, and
• perform inversion calculation on a signal obtained by the calculation of the exclusive OR by the second exclusive NOR circuit;
• a second exclusive OR circuit configured to calculate an exclusive OR of the first signal and the selection signal;
• (L−1) adders, each configured to calculate a different bit of the Gray code by an addition operation based on a carry signal input to the corresponding adder;
• a circuit block configured to
• generate a carry signal to be input to a first adder of the (L−1) adders, on a basis of a calculation of a logical product of a signal output from the second exclusive NOR circuit and the second signal, and
• generate carry signals to be individually input to a second adder to an (L−1)th adder of the (L−1) adders, on a basis of a signal output from the second exclusive OR circuit and the second signal;
• a second terminal configured to output the second signal;
• and
• (L−1) third terminals, each configured to output a third signal output from a corresponding one of the (L−1) adders.

A semiconductor integrated circuit generating an L-bit Gray code (where L is an integer larger than or equal to 3) corresponding to a count value of a first clock signal, the semiconductor integrated circuit comprising:

• a first flip-flop including a clock terminal to which the first clock signal is configured to be input, a D terminal, and a Q terminal;
• a second flip-flop including a clock terminal to which the first clock signal is configured to be input, a D terminal, and a Q terminal configured to output a first signal to be input to the D terminal of the first flip-flop;
• a first inverter configured to
• perform inversion calculation on a second signal output from the Q terminal of the first flip-flop, and
• output a third signal to be input to the D terminal of the second flip-flop, the third signal being obtained by the inversion calculation on the second signal;
• (L−1) adders, each configured to calculate a different bit of the Gray code by an addition operation based on a carry signal input to the corresponding adder;
• a circuit block configured to
• generate a carry signal to be input to a first adder of the (L−1) adders, on a basis of a calculation of a logical product of the first signal and the third signal, and
• generate carry signals to be individually input to a second adder to an (L−1)th adder of the (L−1) adders, on a basis of a the first signal and the second signal;
• a first terminal configured to output the first signal;
• and
• (L−1) second terminals, each configured to output a fourth signal output from a corresponding one of the (L−1) adders, wherein
• the (L−1) adders each includes
• a third flip-flop including a clock terminal to which the first clock signal is input, a D terminal, and a Q terminal configured to output the fourth signal, and
• a first exclusive OR circuit configured to
• calculate an exclusive OR of a carry signal input thereto and the fourth signal output from a Q terminal of the third flip-flop, and
• input a signal obtained by the calculation of the exclusive OR to the D terminal of the third flip-flop,
• each of the (L−1) second terminals is configured to output the fourth signal from the Q terminal of the third flip-flop of a corresponding one of the (L−1) adders, and wherein,
• the semiconductor integrated circuit further comprises:
• a second exclusive OR circuit configured to calculate an exclusive OR of the fourth signal output from the Q terminal of the third flip-flop in the (L−1)th adder and the fourth signal output from the Q terminal of the third flip-flop in an (L−2)th adder of the (L−1) adders;
• and
• a first AND circuit configured to calculate a logical product of a fifth signal output from the second exclusive OR circuit and a sixth signal output from the circuit block as a carry signal for the (L−1)th adder, and
• the first exclusive OR circuit in the (L−1)th adder is configured to calculate an exclusive OR of a signal output from the first AND circuit and the fourth signal output from the Q terminal of the third flip-flop in the (L−1)th adder.