Capacitor voltage balancing techniques for multi-level dual active bridge converter

A multilevel dual active bridge converter configured for balancing capacitor voltage, the multilevel dual active bridge converter comprising:

• a first full bridge circuit having a first plurality of electronic switches, the first full bridge circuit configured to generate a first group of three voltage levels including a first DC voltage level, a one-half first DC voltage level, and a first zero voltage level;
• a second full bridge circuit including a second plurality of electronic switches, the second full bridge circuit configured to generate a second group of three voltage levels including a second DC voltage level, a one-half second DC voltage level, and a second zero voltage level;
• a transformer coupled between the first full bridge circuit and the second full bridge circuit;
• an inductor coupled between the first full bridge circuit and a primary winding of the transformer;
• and
• a control circuit configured for:
• determining a first capacitor voltage difference between a first capacitor voltage and a second capacitor voltage of the first full bridge circuit;
• determining a first zero voltage level correction value based on the first capacitor voltage difference;
• adjusting an internal phase shift value corresponding to a duration of the first zero voltage level based on the first zero voltage level correction value;
• and
• adjusting, based on the adjusted internal phase shift value corresponding to a duration of the first zero voltage level, a timing of the first plurality of electronic switches to reduce the first capacitor voltage difference between the first capacitor voltage and the second capacitor voltage of the first full bridge circuit.

A control circuit configured for balancing capacitor voltage in a multilevel dual active bridge converter, wherein the dual active bridge converter includes a first full bridge circuit having a first plurality of electronic switches, the first full bridge circuit configured to generate a first group of three voltage levels including a first DC voltage level, a one-half first DC voltage level, and a first zero voltage level, a second full bridge circuit including a second plurality of electronic switches, the second full bridge circuit configured to generate a second group of three voltage levels including a second DC voltage level, a one-half second DC voltage level, and a second zero voltage level, a transformer coupled between the first full bridge circuit and the second full bridge circuit, and an inductor coupled between the first full bridge circuit and a primary winding of the transformer, the control circuit configured to perform operations comprising:

• determining a first capacitor voltage difference between a first capacitor voltage and a second capacitor voltage of the first full bridge circuit;
• determining a first zero voltage level correction value based on the first capacitor voltage difference;
• adjusting an internal phase shift value corresponding to a duration of the first zero voltage level based on the first zero voltage level correction value;
• and
• adjusting, based on the adjusted internal phase shift value corresponding to a duration of the first zero voltage level, a timing of the first plurality of electronic switches to reduce the first capacitor voltage difference between the first capacitor voltage and the second capacitor voltage of the first full bridge circuit.