Semiconductor package and method of manufacturing the same

A semiconductor package comprising:

• a base structure comprising a lower surface with a lower connection pad thereon, and an upper surface with an upper connection pad thereon, wherein the upper connection pad is connected to the lower connection pad;
• a plurality of first semiconductor chips stacked on the base structure in a vertical direction, wherein the plurality of first semiconductor chips comprises an uppermost first semiconductor chip and a lowermost first semiconductor chip, and wherein each of the plurality of first semiconductor chips comprise a first lower pad, a first upper pad, and a through silicon via (TSV) connecting the first lower pad and the first upper pad;
• a second semiconductor chip on the uppermost first semiconductor chip, the second semiconductor chip comprising:
• a second lower pad directly bonded to the first upper pad of the uppermost first semiconductor chip;
• and an upper surface comprising a flat region and an edge region having a rounded shape, wherein the edge region is disposed around the flat region;
• and
• an upper dummy chip on the flat region of the second semiconductor chip, the upper dummy chip comprising an area smaller than an area of the second semiconductor chip and a thickness greater than a thickness of the second semiconductor chip,
• wherein the first lower pad of the lowermost first semiconductor chip is directly connected to the upper connection pad, and
• wherein the first upper pad of each of the plurality of first semiconductor chips, except for the uppermost first semiconductor chip, is directly connected to the first lower pad of another first semiconductor chip, among the plurality of first semiconductor chips, adjacent thereto.

A semiconductor package comprising:

• a base structure comprising a lower surface with a lower connection pad thereon, and an upper surface with an upper connection pad thereon, wherein the upper connection pad is connected to the lower connection pad;
• a plurality of first semiconductor chips stacked on the base structure in a vertical direction, wherein the plurality of first semiconductor chips comprises an uppermost first semiconductor chip and a lowermost first semiconductor chip, and wherein each of the plurality of first semiconductor chips comprise a first lower pad, a first upper pad, and a through silicon via connecting the first lower pad to the first upper pad;
• a second semiconductor chip disposed on the uppermost first semiconductor chip, the second semiconductor chip comprising a second lower pad directly bonded to the first upper pad of the uppermost first semiconductor chip;
• a lower dummy chip disposed on the second semiconductor chip, the lower dummy chip comprising an upper surface, wherein the upper surface comprises a flat region and an edge region having a rounded shape, and wherein the edge region is disposed around the flat region;
• and
• an upper dummy chip disposed on the flat region of the lower dummy chip, the upper dummy chip comprising an area smaller than an area of the lower dummy chip and a thickness greater than a thickness of the second semiconductor chip,
• wherein the first lower pad of the lowermost first semiconductor chip is directly bonded to the first upper pad, and
• wherein the first upper pad of each the plurality of first semiconductor chips, except for the uppermost first semiconductor chip, is directly bonded to the first lower pad of another first semiconductor chip, among the plurality of first semiconductor chips, adjacent thereto.