Semiconductor package having dielectric layer with step difference

A semiconductor package comprising:

• first and second chip structures stacked in a first direction,
• wherein the first chip structure incudes:
• a first semiconductor chip,
• first lower electrode pads electrically connected to the first semiconductor chip,
• a first insulating layer surrounding each of the first lower electrode pads,
• through-electrodes penetrating through at least a portion of the first semiconductor chip,
• first upper electrode pads on the through-electrodes, and
• a first dielectric layer covering a portion of each of the first insulating layer, the first semiconductor chip, the through-electrodes, and the first upper electrode pads on the through-electrodes,
• wherein the second chip structure comprises:
• a second semiconductor chip,
• second electrode pads electrically connected to the second semiconductor chip and the first upper electrode pads on the through-electrodes,
• a second insulating layer surrounding the second electrode pads and contacting the first dielectric layer, and
• a second dielectric layer covering at least a portion of each of the second semiconductor chip and the second insulating layer,
• wherein the first dielectric layer comprises a first portion surrounding at least a portion of a side surface of the first insulating layer and a second portion surrounding a side surface of the first semiconductor chip, and
• wherein a first outer surface of the first portion and a second outer surface of the second portion have a step difference.

A semiconductor package comprising:

• a first semiconductor chip;
• first lower electrode pads below the first semiconductor chip and electrically connected to the first semiconductor chip;
• a first insulating layer surrounding a side surface of each of the first lower electrode pads;
• through-electrodes penetrating through at least a portion of the first semiconductor chip and protruding from an upper surface of the first semiconductor chip;
• first upper electrode pads on the through-electrodes and electrically connected to the first semiconductor chip through the through-electrodes;
• a first dielectric layer covering a portion of each of the first insulating layer, the first semiconductor chip, the through-electrodes, and the first upper electrode pads;
• a second semiconductor chip on the first dielectric layer;
• second electrode pads on a first surface of the second semiconductor chip and electrically connected to the second semiconductor chip and the first upper electrode pads on the through-electrodes;
• and
• a second insulating layer surrounding side surfaces of the second electrode pads on the first surface of the second semiconductor chip,
• wherein the first dielectric layer comprises a first portion having a first width and a second portion having a second width greater than the first width on the first portion.