US 2025/0096181 A1Published application

Semiconductor device and method of fabricating the same

AssigneeSamsung Electronics Co., Ltd.

InventorsChangbo LEE, KWANHOO SON, JOON SEOK OH

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Abstract

Disclosed are semiconductor devices and methods of fabricating the same. The method comprises providing a carrier substrate that includes a conductive layer, placing a semiconductor die on the carrier substrate, forming an insulating layer to cover the semiconductor die on the carrier substrate, forming a via hole to penetrate the insulating layer at a side of the semiconductor die and to expose the conductive layer of the carrier substrate, performing a plating process in which the conductive layer of the carrier substrate is used as a seed to form a via filling the via hole, forming a first redistribution layer on a first surface of the semiconductor die and the insulating layer, removing the carrier substrate, and forming a second redistribution layer on a second surface of the semiconductor die and the insulating layer, the first surface and the second surface being located opposite each other.

Claims20

Dependent claims

A semiconductor device, comprising:

a lower redistribution layer;
a semiconductor die on the lower redistribution layer;
an insulating layer on the lower redistribution layer, the insulating layer surrounding the semiconductor die;
a via structure that penetrates the insulating layer and is coupled to the lower redistribution layer, the via structure includes a first metal layer, and a second metal layer which is interposed between the first metal layer and the insulating layer;
and
an upper redistribution layer on the insulating layer and the semiconductor die, the upper redistribution layer being coupled to the via structure,
wherein the lower redistribution layer comprises:
a dielectric layer that covers a bottom surface of the insulating layer and a bottom surface of the semiconductor die, the dielectric layer having a recess exposing a bottom surface of the via structure;
a redistribution pattern that penetrates the dielectric layer through the recess and is coupled to the via structure;
and
a third metal layer between the redistribution pattern and the bottom surface of the via structure, the third metal layer being in contact with a bottom surface of the via structure,
wherein the recess has a width which progressively decreases approaches the via structure,
wherein the first metal layer extends beyond the bottom surface of the insulating layer and into the dielectric layer of the lower redistribution layer,
wherein the bottom surface of the first metal layer is exposed with respect to the second metal layer,
wherein the semiconductor die includes a plurality of die pads on the bottom surface of the semiconductor die,
wherein the dielectric layer of the lower redistribution layer fills a space between the insulating layer and the die pads.

13 more elements

A semiconductor device, comprising:

a lower redistribution layer;
a semiconductor die on the lower redistribution layer;
an insulating layer on the lower redistribution layer, the insulating layer surrounding the semiconductor die;
a via that penetrates the insulating layer and is coupled to a redistribution pattern of the lower redistribution layer, the via includes a first metal layer, and a second metal layer which is interposed between the first metal layer and the insulating layer;
and
an upper redistribution layer on the insulating layer and the semiconductor die, the upper redistribution layer being coupled to the via,
wherein the lower redistribution layer includes:
a dielectric layer that covers a bottom surface of the insulating layer and a bottom surface of the semiconductor die;
and
the redistribution pattern that penetrates the dielectric layer and is coupled to the via,
wherein the via extends beyond the bottom surface of the insulating layer and into the lower redistribution layer, and the via is in contact with an upper surface of the redistribution pattern,
wherein a width of the redistribution pattern decreases as the redistribution pattern approaches the insulating layer,
wherein the bottom surface of the semiconductor die is at a level higher than a level of the bottom surface of the insulating layer, and
wherein, on the bottom surface of the semiconductor die, the dielectric layer of the lower redistribution layer is in contact with a lateral surface of the insulating layer.

11 more elements

A semiconductor device, comprising:

a lower package;
and
an upper package on the lower package,
wherein the lower package includes:
a lower redistribution layer;
a semiconductor die on the lower redistribution layer;
an insulating layer on the lower redistribution layer, the insulating layer surrounding the semiconductor die;
a via that penetrates the insulating layer and is coupled to a lower redistribution pattern of the lower redistribution layer;
a seed layer between the via and the insulating layer, the seed layer surrounding a lateral surface of the via;
an upper redistribution layer on the insulating layer and the semiconductor die, the upper redistribution layer being coupled to the via,
wherein the lower redistribution layer includes:
a lower dielectric layer that covers a bottom surface of the insulating layer and a bottom surface of the semiconductor die;
and
the lower redistribution pattern that penetrates the lower dielectric layer and is coupled to the via,
wherein the upper package is mounted on the upper redistribution layer,
wherein a width of the lower redistribution pattern decreases as the lower redistribution pattern approaches the insulating layer,
wherein the upper redistribution layer includes:
an upper dielectric layer that covers an upper surface of the insulating layer;
and
an upper redistribution pattern that penetrates the upper dielectric layer and is coupled to the via,
wherein a width of the upper redistribution pattern decreases as the upper redistribution pattern approaches the insulating layer,
wherein a bottom surface of the via is exposed with respect to the seed layer,
wherein the bottom surface of the semiconductor die is at a level higher than a level of the bottom surface of the insulating layer, and
wherein the lower dielectric layer is in contact with the bottom surface of the semiconductor die.

21 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/969,410Filed 5 Dec 2024
Priority: KR 10-2020-00127623 Feb 2020
Published: 20 Mar 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification22 codes

H10W 74/017
Using moulds: auxiliary layers for moulds, e.g. release layers or layers preventing residue
H10P 72/74
For supporting or gripping: using temporarily an auxiliary support
H10W 20/042
Of conductive barrier, adhesion or liner layers: the barrier, adhesion or liner layers being seed or nucleation layers
H10W 20/42
Characterised by their conductive parts: vias, e.g. via plugs

Family

Application17/070,540Continuation · filed 14 Oct 2020
Application18/143,983Continuation · filed 5 May 2023
Application18/969,410Continuation
US 11,682,648 B2Related patent
US 12,199,060 B2Related patent
US 2021/0242158 A1Published application
US 2023/0387059 A1Published application
US 2025/0096181 A1This patent

From the US filing history. Foreign family members aren’t listed.

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