Semiconductor package and method for manufacturing the same

A semiconductor package comprising:

• a first redistribution layer structure;
• a first semiconductor die on the first redistribution layer structure;
• a second semiconductor die on the first redistribution layer structure and adjacent to the first semiconductor die;
• a plurality of first connection members on the first redistribution layer structure, and around the first semiconductor die and the second semiconductor die;
• a first molding material on the first redistribution layer structure, the first molding material covering the first semiconductor die and the second semiconductor die, and the first molding material at least partially surrounding the plurality of first connection members;
• a second redistribution layer structure on the first molding material, the second redistribution layer structure connected to the first redistribution layer structure through the plurality of first connection members;
• a third semiconductor die on the second redistribution layer structure;
• a fourth semiconductor die on the second redistribution layer structure;
• a dummy structure on the second redistribution layer structure, and between the third semiconductor die and the fourth semiconductor die;
• and
• a second molding material on the second redistribution layer structure and at least partially surrounding the third semiconductor die, the fourth semiconductor die, and the dummy structure.

A manufacturing method of a semiconductor package comprising:

• forming a first redistribution layer structure on a carrier;
• forming a plurality of connection members on the first redistribution layer structure;
• providing a first set of semiconductor dies on the first redistribution layer structure;
• molding the plurality of connection members and the first set of semiconductor dies with a first molding material on the first redistribution layer structure;
• forming a second redistribution layer structure on the first molding material;
• providing a dummy structure on the second redistribution layer structure;
• and
• providing a second set of semiconductor dies on the second redistribution layer structure,
• wherein the dummy structure is provided between a first semiconductor die of the second set of semiconductor dies and a second semiconductor die of the second set of semiconductor dies.