Methods for bonding wafers of known good dies, and assemblies resulting from such methods

A semiconductor device assembly, comprising:

• a plurality of core dies, each core die having an active side facing downward, and each core die being surrounded peripherally by a first silicon oxide material that is coplanar with the active and a back side of the core die, the plurality of core dies connected in a vertical stack by hybrid bonds between adjacent core dies of the plurality;
• a top die disposed over the plurality of core dies and hybrid bonded to a top one of the plurality of core dies, the top die having an active side facing downward, and the top die being surrounded peripherally by a second silicon oxide material that is coplanar with the active side of the top die and overlapping a back side of the top die, the second silicon oxide material being fusion bonded to the first silicon oxide material;
• and
• a dummy silicon chip disposed over the top die and fusion bonded to the second oxide material overlapping the top die, the dummy silicon chip having sidewalls that are coplanar with outer edges of the peripheral first and second silicon oxide materials.

A semiconductor device assembly, comprising:

• a first semiconductor die having an active side facing downward and being surrounded peripherally by a first silicon oxide material that is coplanar with the active and a back side of the first semiconductor die;
• a second semiconductor die disposed over and hybrid bonded to the first semiconductor die, the second semiconductor die having an active side facing downward and being surrounded peripherally by a second silicon oxide material that is coplanar with the active side of the second semiconductor die and that overlaps a back side of the second semiconductor die, the second silicon oxide material being fusion bonded to the first silicon oxide material;
• and
• a dummy silicon chip disposed over the second semiconductor die and fusion bonded to the second oxide material overlapping the second semiconductor die, the dummy silicon chip having sidewalls that are coplanar with outer edges of the peripheral first and second silicon oxide materials.