Bottom contact jumpers for stacked field effect transistor semiconductors

A semiconductor structure comprising:

• a stacked field effect transistor (FET) comprising a top FET and a bottom FET;
• a bottom source/drain (S/D) contact jumper connection disposed within a gate cut region, wherein the gate cut region comprises a first liner spacer and a dielectric fill disposed within the first liner spacer, and wherein the bottom S/D contact jumper is formed within the dielectric fill;
• a top S/D contact fly-over disposed over a bottom S/D contact in contact with the bottom S/D contact jumper;
• a top S/D access metal track disposed over the bottom S/D contact through the top S/D contact;
• a first gate cut liner facing the top S/D contact fly-over, wherein the first gate cut liner is recessed;
• and
• a second gate cut liner facing a non-fly-over top S/D contact, wherein the second gate cut liner is partially recessed.

A method for fabricating a semiconductor structure, the method comprising:

• forming a top field effect transistor (FET) comprising a top gate, over a bottom FET comprising a bottom gate, wherein the top FET is in contact with a top source/drain (S/D) epitaxial, and wherein the bottom FET is in contact with a bottom S/D epitaxial;
• forming a cut region at a boundary to a cell comprising the top FET and bottom FET;
• forming a first liner spacer in the cut region;
• perform a dielectric fill in the first liner spacer;
• forming a bottom S/D contact jumper in the dielectric fill;
• forming a bottom S/D contact with a contact recess;
• and
• forming a top S/D contact fly-over over the bottom S/D contact, wherein the bottom S/D contact is in contact with the bottom S/D contact jumper.