Transistor device with reduced on-resistance

A method for forming a transistor device, the method comprising:

• forming first trenches and second trenches in a semiconductor body and each extending from a first surface of the semiconductor body into the semiconductor body;
• forming a drift region adjoining each of the second trenches;
• forming source regions separated from the drift region by a respective body region;
• and
• forming gate electrodes in the first trenches adjacent to at least one of the body regions and dielectrically insulated from the at least one of the body regions by a gate dielectric,
• wherein forming the second trenches comprises forming the second trenches such that each of the second trenches is configured to induce a strain in regions of the drift region adjoining the respective second trench,
• wherein forming the second trenches further comprises at least partially filling the second trenches with a strain inducing material such that at least sidewalls and a bottom of each of the second trenches are covered by a strain inducing material.