A semiconductor memory device, comprising:
- a first conductor layer provided via a first insulator layer above a substrate;
- a stacked structure in which a plurality of second conductor layers are stacked above the first conductor layer and spaced apart from each other in a first direction;
- a pillar passing through the second conductor layers along the first direction, and including a first semiconductor layer electrically coupled to the first conductor layer and a second insulator layer provided between the first semiconductor layer and the second conductor layers of the stacked structure, intersections of the pillar with the second conductor layers functioning as memory cell transistors;
- a plurality of insulating members provided in a plurality of slits each extending in a second direction intersecting the first direction in the second conductor layers of the stacked structure and dividing the stacked structure into a plurality of regions in a third direction intersecting the first direction and the second direction;
- a plurality of conductive members passing through the second conductor layers along the first direction in which top surfaces thereof differing in height from a top surface of the pillar, each of the conductive members including a third conductor layer partially in contact with the first conductor layer and a third insulator layer provided between the third conductor layer and the second conductor layers of the stacked structure;
- and
- a plurality of upper contacts provided on third conductor layers of first and second conductive members among the conductive members, the first and second conductive members being aligned in the second direction,
- wherein no upper contact is provided on third conductor layers of third and fourth conductive members among the conductive members, the third and fourth conductive members being aligned in the second direction, and
- the first to fourth conductive members are arranged within a region between two insulating members adjacent in the third direction among the insulating members, positions of the first and second conductive members being closer to a central position between the two insulating members than positions of the third and fourth conductive members along the third direction.