Wafer-level power module and manufacturing method therefor

A wafer-level power module comprises:

• a wafer, the wafer comprising a wafer functional area, and the wafer functional area being located on a first surface of the wafer;
• and
• a passive element, the passive element comprising at least one functional conductive layer and a functional dielectric layer, wherein:
• the passive element and the wafer are stacked, and an occupied area after stacking is equal to an area of the wafer;
• the wafer functional area is electrically connected with the functional conductive layer through a conductive path, at least one part of the conductive path is realized by electroplating a through hole or a semi-through hole, and the conductive path is arranged on a side surface or a middle position of the wafer-level power module;
• the wafer is attached to or directly attached to the passive element by means of a filling material, and the passive element provides mechanical strength support for the wafer;
• and
• the functional dielectric layer is disposed between the at least one functional conductive layer of the passive element and the first surface of the wafer.

A method for manufacturing a wafer-level power module, comprising the following steps:

• a step S1:
• providing a wafer;
• a step S2:
• forming TSV holes in a substrate of the wafer, wherein in the step S2, the TSV holes do not penetrate through the substrate of the wafer;
• a step S3:
• forming a first insulating layer on an inner wall of each TSV hole;
• a step S4:
• filling a metal in each TSV hole, and forming a first metal layer on a first surface of the substrate of the wafer;
• a step S5, thinning a second surface of the wafer, exposing the metal in each TSV hole, and leaving a space to a passive element;
• a step S6:
• providing the passive element on the second surface of the wafer;
• a step S7, scribing to form an independent power module, wherein the plane size of the power module is the same as the plane size of the wafer.

A method for manufacturing a wafer-level power module, comprising the following steps:

• a step S1:
• providing a wafer;
• a step S2, forming a first metal layer on a first surface of the wafer, wherein a first surface of the wafer is a functional surface;
• a step S3, after the first surface of the wafer is fixed on a carrier, thinning the wafer, and leaving a space to a passive element;
• a step S4:
• forming a TSV hole from a second surface of the wafer to an inside, the TSV hole extending to the first metal layer;
• a step S5:
• forming a first insulating layer on an inner wall of the TSV hole and the second surface of the wafer;
• a step S6:
• filling the TSV hole with a metal, and forming a second metal layer on the second surface of the wafer;
• a step S7:
• providing the passive element on the second surface of the wafer;
• and
• a step S8:
• scribing to form an independent power module, wherein the plane size of the power module is the same as the plane size of the wafer.

A method for manufacturing a wafer-level power module, comprising the following steps:

• a step S1:
• providing a wafer;
• a step S2:
• laying a passive element on a second surface of the wafer;
• a step S3:
• forming a conductive hole, the conductive hole penetrating through the wafer and the passive element;
• a step S4:
• forming a first insulating layer in the conductive hole;
• a step S5:
• drilling a deep drilling hole on a surface of the passive element, and forming a conductive hole with a wider width at one end of the conductive hole;
• a step S6:
• forming a metal layer on a first surface of the wafer, the surface of the passive element and the conductive hole;
• a step S7:
• etching for respectively forming required pins on the first surface of the wafer and the surface of the passive element;
• a step S8:
• scribing is carried out at a position of the conductive hole to form an independent power module, and the plane size of the power module is the same as the plane size of the wafer.

A method for manufacturing a wafer-level power module, comprising the following steps:

• a step S1:
• providing a wafer;
• a step S2, laying a passive element on a second surface of the wafer, wherein an internal metal layer is arranged in the passive element;
• a step S3:
• forming a conductive hole from a first surface of the wafer to an inside, so that the internal metal layer is exposed;
• a step S4:
• forming a first insulating layer in the conductive hole;
• a step S5:
• removing a part of the first insulating layer located outside the internal metal layer, so that a part of the internal metal layer is exposed;
• a step S6:
• filling a metal in the conductive hole, and forming a metal layer on the first surface of the wafer;
• a step S7:
• etching for forming a required pin on the first surface of the wafer;
• a step S8:
• scribing at a position of the conductive hole to form an independent power module, the plane size of the power module being the same as the plane size of the wafer.