Semiconductor package

A semiconductor package comprising:

• a lower redistribution structure;
• a lower chip structure including a first semiconductor chip on the lower redistribution structure, a second semiconductor chip on the first semiconductor chip, a first encapsulant surrounding the second semiconductor chip, and a plurality of first posts passing through the first encapsulant, the plurality of first posts electrically connected to the first semiconductor chip;
• a second encapsulant on the lower redistribution structure and surrounding the lower chip structure;
• a plurality of second posts passing through the second encapsulant, wherein the plurality of second posts are electrically connected to the lower redistribution structure;
• an upper redistribution structure on the second encapsulant;
• and
• an upper chip structure mounted on the upper redistribution structure,
• wherein the plurality of first posts provide a transmission path for a signal between the lower chip structure and the upper chip structure.

A semiconductor package comprising:

• a lower redistribution structure;
• a lower chip structure including a plurality of semiconductor chips on the lower redistribution structure and a plurality of first posts on a lowermost semiconductor chip, among the plurality of semiconductor chips, wherein the plurality of first posts are spaced apart from chips other than the lowermost semiconductor chip;
• a plurality of second posts on the lower redistribution structure;
• an encapsulant covering at least a portion of each of the lower chip structure and the plurality of second posts;
• and
• an upper chip structure disposed on the encapsulant and electrically connected to the plurality of first posts and second posts,
• wherein a level of an uppermost end of each of the plurality of first posts is lower than a level of an uppermost end of each of the plurality of second posts.