Stacked via structure disposed on a conductive pillar of a semiconductor die

A stacked via structure, disposed on a surface of a semiconductor die, the stacked via structure comprising:

• a first dielectric layer disposed on the semiconductor die;
• a first conductive via embedded in the first dielectric layer, wherein the first conductive via is in physical contact with the surface of the semiconductor die;
• a second dielectric layer disposed on the first dielectric layer;
• a first redistribution wiring disposed on the first conductive via;
• a second conductive via electrically connected to the first redistribution wiring, wherein the first redistribution wiring and the second conductive via are embedded in the second dielectric layer;
• and
• a second redistribution wiring disposed on the second conductive via, wherein a first bottom width of the first conductive via and the semiconductor die is greater than a second bottom width of the second conductive via and the first redistribution wiring.

A structure, comprising:

• a semiconductor die laterally encapsulated by an insulating encapsulation;
• a redistribution circuit structure, comprising:
• stacked dielectric layers covering the semiconductor die and the insulating encapsulation;
• a bottom tier conductive via embedded in a bottommost dielectric layer among the stacked dielectric layers, wherein the bottom tier conductive via is in physical contact with at least one of the conductive terminals of the semiconductor die;
• a first redistribution wiring disposed on the bottom tier conductive via;
• a top tier conductive via embedded in an upper dielectric layer among the stacked dielectric layers, wherein the top tier conductive via is electrically connected to the at least one of the conductive terminals of the semiconductor die;
• and
• a second redistribution wiring disposed on the top tier conductive via, wherein a first minimum width of the bottom tier conductive via is greater than a second minimum width of the top tier conductive via.