Chip on film package and display apparatus including the same

A chip on film (COF) package comprising:

• a base film including a first bonding region, a second bonding region, and a circuit region between the first bonding region and the second bonding region;
• a plurality of conductive lines on an upper surface of the base film in the circuit region;
• a protection layer covering the plurality of conductive lines on the upper surface of the base film;
• a semiconductor chip on the upper surface of the base film in the circuit region, the semiconductor chip connected with one end of a first group of conductive lines among the plurality of conductive lines;
• a plurality of first bridge patterns on the upper surface of the base film in the first bonding region, the plurality of first bridge patterns arranged in parallel in a first horizontal direction and connected with an other end of the first group of conductive lines;
• a first interlayer insulation layer covering the plurality of first bridge patterns on the upper surface of the base film in the first bonding region;
• and
• a plurality of input pads on the first interlayer insulation layer and arranged in zigzag in the first horizontal direction, and the plurality of input pads respectively being connected with the plurality of first bridge patterns.

A chip on film (COF) package comprising:

• a base film including a first bonding region, a second bonding region, and a circuit region between the first bonding region and the second bonding region;
• a semiconductor chip on the base film in the circuit region;
• a plurality of bridge patterns on the base film in the first bonding region;
• a plurality of output pads on the base film in the second bonding region;
• a plurality of conductive lines on the base film in the circuit region,
• the plurality of conductive lines including a plurality of input lines respectively connecting the semiconductor chip with the plurality of bridge patterns, a plurality of output lines respectively connecting the semiconductor chip with the plurality of output pads, and a plurality of bypass lines respectively connecting the plurality of bridge patterns with the plurality of output pads;
• a protection layer on the base film and covering the plurality of conductive lines in the circuit region;
• an interlayer insulation layer on the base film and covering the plurality of bridge patterns in the first bonding region;
• and
• a plurality of input pads on the interlayer insulation layer and respectively connected with the plurality of bridge patterns.