SRAM Middle Strap with Feedthrough Via

An integrated circuit, comprising:

• a first SRAM cell and a second SRAM cell, each including a plurality of field-effect transistors (FETs);
• a front metal line over the FETs and a back metal line below the FETs;
• and
• a middle strap area disposed between the first SRAM cell and the second SRAM cell,
• wherein the middle strap area includes:
• a plurality of gate stacks extending lengthwise along a direction,
• a gate isolation structure extending through a gate stack of the plurality of gate stacks,
• a feedthrough via (FTV) embedded in the gate isolation structure, wherein the FTV electrically couples the front metal line and the back metal line,
• a first dielectric gate disposed between the FTV and the first SRAM cell, and
• a second dielectric gate disposed between the FTV and the second SRAM cell.

An integrated circuit, comprising:

• a first SRAM cell and a second SRAM cell, wherein the first SRAM cell includes a device;
• and
• a middle strap area disposed between the first SRAM cell and the second SRAM cell,
• wherein the middle strap area includes:
• a plurality of gate stacks extending lengthwise along a first direction,
• a gate isolation structure extending through a gate stack of the plurality of gate stacks,
• a feedthrough via (FTV) enclosed by the gate isolation structure from a top view, and
• a first active region and a second active region disposed on two sides of the FTV and extending lengthwise along a second direction perpendicular to the first direction,
• wherein the first active region and the second active region span from the first SRAM cell to the second SRAM cell, and
• wherein the FTV connects a front interconnect structure over the device and a back interconnect structure below the device.