Semiconductor package

A semiconductor package comprising:

• a first redistribution structure;
• a first chip on the first redistribution structure;
• a molding member on the first redistribution structure and surrounding the first chip;
• a conductive pillar penetrating through the molding member in a first direction;
• a second redistribution structure on a first surface of the molding member;
• a second chip on the second redistribution structure;
• and
• a heat dissipation chip on the second redistribution structure and spaced apart from the second chip in a second direction that intersects the first direction to at least partially overlap the first chip in the first direction,
• wherein the second redistribution structure comprises a second redistribution insulation layer, a second redistribution pattern, and a heat conduction pattern,
• wherein the second redistribution pattern electrically connects the second chip with the conductive pillar, and
• wherein the heat conduction pattern penetrates through the second redistribution structure in the first direction from the first surface of the molding member to a second surface of the heat dissipation chip.

A semiconductor package comprising:

• a first redistribution structure;
• a first chip on the first redistribution structure;
• a molding member on the first redistribution structure and surrounding the first chip;
• a conductive pillar arranged spaced apart from the first chip in a second direction to penetrate through the molding member in a first direction that intersects the second direction;
• a second redistribution structure on a first surface of the molding member;
• a second chip on the second redistribution structure;
• a heat dissipation chip on the second redistribution structure and spaced apart from the second chip in the second direction to at least partially overlap the first chip in the first direction;
• and
• a thermal interfacial material (TIM) layer between the heat dissipation chip and the second redistribution structure,
• wherein the second redistribution structure comprises a second redistribution insulation layer, a second redistribution pattern, and a heat conduction pattern,
• wherein the heat conduction pattern is electrically disconnected to the first chip,
• wherein the second redistribution pattern electrically connects the second chip to the conductive pillar,
• wherein the heat conduction pattern penetrates through the second redistribution structure in the first direction from the first surface of the molding member to a second surface of the heat dissipation chip, and
• wherein the first chip comprises a logic chip, the second chip comprises a memory chip, and the heat dissipation chip comprises silicon.