Wafer level chip scale package structure and method of manufacturing wafer level chip scale package

Abstract

The present disclosure provides a wafer level chip scale package structure including a wafer in which a plurality of semiconductor devices are arranged, a heat dissipation plate attached to an upper end of the wafer according to positions of the plurality of semiconductor devices, and a sealing resin placed on an upper portion of the heat dissipation plate to be cured and to seal the wafer and the heat dissipation plate, wherein chip scale packages, each including the wafer, the heat dissipation plate, and the sealing resin bonded to each other according to the semiconductor device, are separated from each other. There are effects in that the heat generated during power semiconductor operation may be effectively dissipate through metal and warpage occurring in a large-area wafer may be prevented.

Dependencies are inferred from the claim text.