Test structure for use in dynamic random access memory and manufacturing method thereof

A method of manufacturing a test structure for use in a dynamic random access memory, the method comprising:

• receiving a semiconductor substrate, a first gate structure, a first source/drain region, and a second source/drain region, wherein the first gate structure, the first source/drain region, and the second source/drain region are disposed in the semiconductor substrate, and the first source/drain region and the second source/drain region are at two sides of the first gate structure;
• forming a bit line structure on the first source/drain region;
• forming a dielectric layer on the bit line structure and the semiconductor substrate;
• forming a first contact plug penetrating through the dielectric layer, wherein the first contact plug is in contact with the second source/drain region;
• forming a first landing pad and a second landing pad on the dielectric layer, wherein the first landing pad is on the first contact plug;
• and
• forming a conductive layer on and electrically connected to the first landing pad and the second landing pad, wherein the conductive layer covers a first upper surface of the first landing pad and a second upper surface of the second landing pad and has a portion between the first landing pad and the second landing pad.