Semiconductor wafer fabrication with exposure defined graphene features
AssigneeNXP USA, Inc.
InventorDouglas Michael Reber
Life of this patent
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Abstract
A back-end-of-line integrated circuit is formed on an integrated circuit structure having one or more polymer interlayer dielectric (ILD) layers formed over a first conductive wiring line layer by selectively processing an exposed portion of the one or more polymer ILD layers with application irradiation from a laser or light source to form a graphene interconnect structure in the one or more polymer ILD layers which is directly, electrically connected to the first conductive wiring line layer.
Claims20
A method for making an integrated circuit, comprising:
- providing an integrated circuit structure comprising one or more polymer interlayer dielectric (ILD) layers formed over a first conductive wiring line layer;
- and
- selectively processing an exposed portion of the one or more polymer ILD layers by applying irradiation from a laser or light source to form a graphene interconnect structure in the one or more polymer ILD layers which is directly, electrically connected to the first conductive wiring line layer.
A method for forming a graphene interconnect structure, comprising:
- forming a first conductive layer over a first dielectric layer;
- forming one or more polyimide dielectric layers over the first conductive layer;
- selectively applying irradiation to convert the one or more polyimide dielectric layers into the graphene interconnect structure comprising a graphene wiring line formed in an upper portion of a first polyimide dielectric layer and a graphene via structure formed in the first polyimide dielectric layer to directly, electrically connect the graphene wiring line to the first conductive layer.
An integrated circuit, comprising:
- a substrate comprising one or more semiconductor devices formed therein;
- and
- a multi-layer graphene interconnect stack formed over the substrate comprising a plurality of stacked graphene wiring lines that are vertically separated from one another by a corresponding plurality of polyimide interlayer dielectric (ILD) layers, the multi-layer graphene interconnect stack comprising:
- a first graphene wiring line in a first conductor layer,
- a second graphene wiring line in a second conductor layer that is separated from the first graphene wiring line by a first polyimide ILD layer, and
- a first graphene via structure formed in the first polyimide ILD layer to electrically connect the first graphene wiring line to the second graphene wiring line;
- where the first graphene wiring line, second graphene wiring line, and first graphene via structure each comprise a graphene foam structure which does not include an underlying metal layer.
Dependencies are inferred from the claim text.