Selective deposition of graphene on cobalt-capped copper dual damascene interconnect

A semiconductor device comprising:

• a first dielectric layer having a via;
• a liner layer conformally lining sidewalls of the via;
• a copper material formed over the liner layer in the via, the copper material having an exposed copper surface planar with a planar surface of the first dielectric layer;
• a cobalt cap formed directly on the exposed copper surface, the cobalt cap having an exposed cobalt surface;
• a carbon cap selectively formed directly on the exposed cobalt surface relative to the first dielectric layer;
• and
• a second dielectric layer formed over the carbon cap and the first dielectric layer,
• wherein the cobalt cap is disposed between the copper material and the carbon cap.