Gate electrode deposition in stacking transistors and structures resulting therefrom

A method comprising:

• forming a dummy gate stack around a plurality of nanostructures over a substrate, wherein the plurality of nanostructures are alternatingly stacked with a plurality of dummy nanostructures;
• forming lower source/drain regions over the substrate, wherein lower nanostructures of the plurality of nanostructures extend between the lower source/drain regions;
• forming upper source/drain regions over the lower source/drain regions, wherein upper nanostructures of the plurality of nanostructures extend between the upper source/drain regions;
• removing the dummy gate stack and the plurality of dummy nanostructures to define an opening;
• and
• performing a first deposition process to form a lower work function metal (WFM) layer in the opening around the plurality of nanostructures, wherein an initial deposition cycle of the first deposition process comprises:
• flowing a first precursor in the opening, wherein the first precursor attaches to upper surfaces in the opening;
• after flowing the first precursor, flowing a second precursor in the opening, wherein the second precursor attaches to lower surfaces in the opening, and wherein the first precursor has a higher sticking coefficient than the second precursor;
• and
• flowing a third precursor in the opening, wherein the third precursor reacts with the second precursor at a greater rate than the third precursor reacts with the first precursor.

A semiconductor device comprising:

• lower nanostructures extending between lower source/drain regions;
• upper nanostructures extending between upper source/drain regions, wherein the upper nanostructures is disposed over the lower nanostructures, and wherein the upper source/drain regions is disposed over the lower source/drain regions;
• a lower gate electrode around the lower nanostructures, wherein the lower gate electrode comprises a halide residue, and wherein a concentration of halide residue in the lower gate electrode decreases in a direction towards a bottom surface of the lower gate electrode;
• and
• an upper gate electrode around the upper nanostructures, wherein the upper gate electrode is disposed over the lower gate electrode.