Conductance modulation in computational memory

A system comprising:

• a memory device including:
• a plurality of unit cells arranged in a crossbar arrangement, wherein the plurality of unit cells comprises non-volatile memory (NVM) devices;
• and
• a plurality of access transistors connected to the plurality of unit cells;
• a controller configured to:
• determine a plurality of conductance values for the plurality of unit cells, wherein the plurality of conductance values are less than maximum conductance values of the plurality of unit cells;
• determine a read gate voltage for driving the plurality of access transistors to read from the plurality of unit cells;
• and
• map a plurality of weights to the plurality of conductance values and to the read gate voltage.

A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions readable by a device to cause the device to:

• determining a plurality of conductance values for a plurality of unit cells arranged in a crossbar arrangement, wherein the plurality of unit cells comprises non-volatile memory (NVM) devices, and the plurality of conductance values are less than maximum conductance values of the plurality of unit cells;
• determining a read gate voltage for driving a plurality of access transistors to read from the plurality of unit cells;
• and
• mapping a plurality of weights to the plurality of conductance values and to the read gate voltage.