Semiconductor memory device and memory system

Abstract

A semiconductor memory device includes a memory cell array, a control circuit, and a voltage generation circuit. The control circuit is configured to perform a first operation to access the memory cell array and then a second operation to access the memory cell array. The voltage generation circuit is configured to generate a first operation voltage, which is supplied from an output terminal of the voltage generation circuit to the memory cell array during the first operation, and a second operation voltage, which is supplied from the output terminal to the memory cell array during the second operation. The control circuit is configured to control the voltage generation circuit to maintain a voltage output from the output terminal to be at the first operation voltage after the first operation until the second operation voltage starts to be supplied to the memory cell array for the second operation.

Dependencies are inferred from the claim text.