Semiconductor memory device

A memory system comprising:

• a semiconductor memory device;
• and
• a memory controller,
• wherein:
• the semiconductor memory device includes:
• a first plane including a plurality of first blocks, each of the first blocks including a first memory cell;
• a second plane including a plurality of second blocks, each of the second blocks including a second memory cell;
• a voltage generator which includes a first driver configured to supply power to the first plane and a second driver configured to supply power to the second plane;
• an input/output circuit configured to receive a command set from the memory controller;
• and
• a sequencer configured to execute an operation in response to the command set,
• the memory controller is configured to send the command set to the semiconductor memory device,
• when the memory controller sends a first command set that instructs execution of a first operation to the first memory cell of one of the first blocks, the sequencer of the semiconductor memory device executes the first operation, the first operation causing a change of a threshold voltage of the first memory cell of the one of the first blocks,
• when the memory controller sends a second command set that instructs execution of a second operation to the second memory cell of one of the second blocks during execution of the first operation, the sequencer of the semiconductor memory device executes the second operation in parallel with the first operation, and
• when the memory controller sends a third command set that instructs execution of a third operation to the first memory cell of another one of the first blocks during execution of the first operation, the sequencer of the semiconductor memory device suspends the first operation, executes the third operation, and resumes the first operation upon completion of the third operation.