Memory device and operating method of the memory device
AssigneeSK hynix Inc.
InventorsNam Cheol JEON, Chang Beom WOO
Life of this patent
Estimating the term…
Abstract
An embodiment of the present disclosure relates to a memory device configured to: apply an erase voltage and a first pass voltage at a first time, apply a turn-on voltage at a second time before a level of the erase voltage increases to a target level, maintain the erase voltage, the first pass voltage, and the turn-on voltage at a third time when the level of the erase voltage equals the target level, and reduce a voltage difference between a memory cell and a word line at a fourth time after the third time.
Claims13
A memory device, comprising:
- a first select transistor, a memory cell, and a second select transistor coupled in series between a source line and a bit line;
- and
- a peripheral circuit configured to perform an erase operation on the memory cell,
- wherein the peripheral circuit is configured to, during the erase operation:
- apply an erase voltage to the source line and the bit line and a first pass voltage to a word line coupled to the memory cell at a first time,
- apply a turn-on voltage to a first select line coupled to the first select transistor and a second select line coupled to the second select transistor at a second time before a level of the erase voltage applied to the source line and the bit line increases to a target level,
- erase the memory cell by maintaining the erase voltage, the first pass voltage, and the turn-on voltage at a third time when the level of the erase voltage applied to the source line and the bit line equals the target level, and
- erase the memory cell by reducing a voltage difference between the memory cell and the word line at a fourth time after the third time.
A method of operating a memory device, the method comprising:
- applying an erase voltage to a source line and a bit line, applying a turn-off voltage to first and second select lines between the source line and the bit line, and applying a first pass voltage to a word line between the first and second select lines;
- applying a turn-on voltage to the first and second select lines before a level of the erase voltage equals a target level;
- and
- applying a second pass voltage greater than the first pass voltage to the word line after a predetermined time from a time when the level of the erase voltage equals the target level.
A method of operating a memory device, the method comprising:
- applying an erase voltage to a source line and a bit line, applying a turn-off voltage to first and second select lines between the source line and the bit line, and applying a pass voltage to a word line between the first and second select lines;
- applying a turn-on voltage to the first and second select lines before a level of the erase voltage equals a target level;
- and
- floating the word line after a predetermined time from a time when the level of the erase voltage equals the target level.
Dependencies are inferred from the claim text.