Memory device, operation method thereof, and memory system

A memory system comprising:

• one or more memory devices, each of the memory devices comprising:
• a memory cell array comprising a first memory deck and a second memory deck stacked with each other, wherein the first memory deck and the second memory deck both comprise a plurality of memory cell layers and a word line layer corresponding to each memory cell layer, and at least one dummy memory cell layer and a dummy word line layer corresponding to each dummy memory cell layer are provided at a junction position of the first memory deck and the second memory deck;
• and
• a peripheral circuit coupled to the memory cell array and configured to:
• when performing a program operation on a selected memory cell layer in the first memory deck, apply a program voltage to a word line layer corresponding to the selected memory cell layer and apply a first pass voltage to a word line layer corresponding to an unselected memory cell layer in the first memory deck;
• apply a second pass voltage to the word line layer corresponding to the plurality of memory cell layers in the second memory deck;
• and
• apply a third pass voltage to the dummy word line layer corresponding to the at least one dummy memory cell layer at the junction position of the first memory deck and the second memory deck, wherein
• the third pass voltage is less than the second pass voltage, and the second pass voltage is less than the first pass voltage;
• and
• a memory controller coupled to the one or more memory devices and configured to control the one or more memory devices.

An operation method of a memory device, comprising:

• when performing a program operation on a selected memory cell layer in a first memory deck of a memory cell array of the memory device, applying a program voltage to a word line layer corresponding to the selected memory cell layer and applying a first pass voltage to a word line layer corresponding to an unselected memory cell layer in the first memory deck;
• applying a second pass voltage to a word line layer corresponding to a plurality of memory cell layers in a second memory deck which is stacked with the first memory deck;
• and
• applying a third pass voltage to a dummy word line layer corresponding to at least one dummy memory cell layer at a junction position of the first memory deck and the second memory deck, wherein
• the third pass voltage is less than the second pass voltage, and the second pass voltage is less than the first pass voltage.