Semiconductor memory device

A semiconductor memory device comprising:

• a substrate;
• a plurality of conductive layers arranged in a first direction intersecting a surface of the substrate;
• a semiconductor layer extending in the first direction and facing the plurality of conductive layers;
• an electric charge accumulating layer provided between the plurality of conductive layers and the semiconductor layer;
• a bit line electrically connected to one end portion in the first direction of the semiconductor layer;
• and
• a control circuit electrically connected to the plurality of conductive layers and the bit line, wherein
• the plurality of conductive layers include a first conductive layer and a second conductive layer adjacent in the first direction to the first conductive layer,
• the control circuit is configured capable of executing a write operation,
• the write operation includes a plurality of write loops,
• the plurality of write loops each include:
• a first program operation that applies the first conductive layer with a program voltage, applies the second conductive layer with a write pass voltage smaller than the program voltage, and applies the bit line with a first bit line voltage;
• a second program operation that applies the first conductive layer with the program voltage, applies the second conductive layer with the write pass voltage, and applies the bit line with a second bit line voltage larger than the first bit line voltage;
• and
• a verify operation that applies the first conductive layer with a verify voltage and applies the second conductive layer with a read pass voltage smaller than the program voltage,
• the program voltage increases an offset voltage at a time along with increase in the number of times of executions of the write loop,
• the write operation includes a state judging operation that judges whether a memory cell corresponding to the semiconductor layer and the second conductive layer is controlled to a Low-state, or not,
• the verify operation executes verification at a first sense level, executes verification at a second sense level larger than the first sense level, and executes verification at a third sense level larger than the second sense level,
• when a result of verification at the first sense level is a verify FAIL, the first program operation is executed,
• when a result of verification at the first sense level is a verify PASS and the memory cell is not controlled to the Low-state, the second program operation is executed until a result of verification at the second sense level becomes a verify PASS, and
• when a result of verification at the first sense level is a verify PASS and the memory cell is controlled to the Low-state, the second program operation is executed until a result of verify at the third sense level becomes a verify PASS.

A semiconductor memory device comprising:

• a substrate;
• a plurality of conductive layers arranged in a first direction intersecting a surface of the substrate;
• a semiconductor layer extending in the first direction and facing the plurality of conductive layers;
• an electric charge accumulating layer provided between the plurality of conductive layers and the semiconductor layer;
• a bit line electrically connected to one end portion in the first direction of the semiconductor layer;
• and
• a control circuit electrically connected to the plurality of conductive layers and the bit line, wherein
• the plurality of conductive layers include a first conductive layer and a second conductive layer adjacent in the first direction to the first conductive layer,
• a first memory cell is provided corresponding to the first conductive layer and the semiconductor layer,
• a second memory cell is provided corresponding to the second conductive layer and the semiconductor layer,
• the control circuit is configured capable of executing a write operation,
• the write operation includes a plurality of write loops,
• the plurality of write loops each include:
• a first program operation that applies the first conductive layer with a program voltage, applies the second conductive layer with a write pass voltage smaller than the program voltage, and applies the bit line with a first bit line voltage;
• and
• a second program operation that applies the first conductive layer with the program voltage, applies the second conductive layer with the write pass voltage, and applies the bit line with a second bit line voltage larger than the first bit line voltage,
• the program voltage increases an offset voltage at a time along with increase in the number of times of executions of the write loop,
• the write operation includes a state judging operation that judges whether a second memory cell is controlled to a Low-state, or not,
• when the second memory cell is controlled to the Low-state, the first program operation is executed, and
• when the second memory cell is not controlled to the Low-state, the second program operation is executed.