A semiconductor memory device, comprising:
- a conductive region having a surface extending in a first direction and a second direction and facing a third direction, the first to third directions crossing one another;
- a first select gate line extending in the first direction and the second direction and being provided above the conductive region in the third direction;
- a first word line extending in the first direction and the second direction and being provided above the first select gate line in the third direction;
- a second word line extending in the first direction and the second direction and being provided above the first word line in the third direction;
- a third word line extending in the first direction and the second direction and being provided above the second word line in the third direction;
- a second select gate line extending in the first direction and the second direction and being provided above the third word line in the third direction;
- a bit line extending in the first direction and being provided above the second select gate line in the third direction;
- and
- a first memory string extending in the third direction and connected between the bit line and the conductive region, the first memory string including
- a first select transistor to a gate of which the first select gate line is connected,
- a first memory cell transistor to a gate of which the first word line is connected,
- a second memory cell transistor to a gate of which the second word line is connected,
- a third memory cell transistor to a gate of which the third word line is connected, and
- a second select transistor to a gate of which the second select gate line is connected;
- a row decoder configured to apply voltages to the first select gate line, the first word line, the second word line, the third word line, and the second select gate line, respectively;
- and
- a sequencer configured to perform
- a first write operation to write data into the third memory cell transistor,
- a second write operation to write data into the second memory cell transistor, after the first write operation is performed, and
- a third write operation to write data into the first memory cell transistor, after the second write operation is performed,
- wherein, in the second write operation, before writing the data into the second memory cell transistor, the row decoder is controlled to:
- at a first timing,
- apply a first voltage to the first select gate line to thereby turn on the first select transistor, and
- apply a second voltage to the first word line to thereby turn on the first memory cell transistor;
- at a second timing after the first timing,
- apply a third voltage lower than the first voltage to the first select gate line to turn off the first select gate transistor;
- at a third timing after the second timing,
- apply a fourth voltage higher than the second voltage to the first word line,
- apply a fifth voltage higher than the second voltage to the second word line, and
- apply a sixth voltage higher than the second voltage to the third word line;
- and
- at a fourth timing after the third timing,
- apply a seventh voltage higher than the fourth to sixth voltages to the second word line.