Non-volatile memory with efficient precharge in sub-block mode

A method of programming memory cells that are positioned in a block, the block is divided into a first sub-block and a second sub-block, comprising:

• ramping up data word lines of the second sub-block to boost channels in the second sub-block to a boosted condition;
• prior to ramping up data word lines of the second sub-block, ramping up data word lines of the first sub-block to boost channels in the first sub-block to the boosted condition and to pre-charge the channels of the second sub-block;
• and
• applying a program voltage to a selected word line of the second sub-block while channels in the first sub-block are boosted and channels in the first sub-block are in the boosted condition.

A non-volatile storage apparatus, comprising:

• a plurality of NAND strings arranged as a block of non-volatile memory cells, the block is divided into a first sub-block and a second sub-block such that each NAND string includes some non-volatile memory cells in the first sub-block and some non-volatile memory cells in the second sub-block;
• a plurality of bit lines connected to the NAND strings such that each bit line is connected to non-volatile memory cells of the first sub-block and to non-volatile memory cells of the second sub-block;
• a plurality of data word lines connected to the NAND strings, a first subset of the data word lines are connected to memory cells of the first sub-block, a second subset of the data word lines are connected to memory cells of the second sub-block;
• a first selection line connected to a first side of the NAND strings, the first sub-block is positioned between the first selection line and the second sub-block;
• a second selection line connected to a second side of the NAND strings opposite the first side of the NAND strings, the second sub-block is positioned between the second selection line and the first sub-block;
• and
• a control circuit connected to the data word lines, the first selection line, the second selection line and the bit lines;
• the control circuit is configured to program non-volatile memory cells of the first sub-block and the second sub-block in a word line direction from second control line toward the first control line, the control circuit is configured to program non-volatile memory cells of the second sub-block by:
• boosting channels of unselected NAND strings in the second sub-block to cause channels of the unselected NAND strings in the second sub-block to increase to a voltage that inhibits programming for memory cells of the unselected NAND strings in the second sub-block and that are connected to a selected data word line,
• prior to the boosting channels of unselected NAND strings in the second sub-block, boosting channels of unselected NAND strings in the first sub-block to cause channels of the unselected NAND strings in the first sub-block to increase to a voltage that inhibits programming for memory cells of the unselected NAND strings in the first sub-block and that are connected to the selected data word line and to cause channels of the unselected NAND strings in the second sub-block to pre-charge prior to the boosting channels of the unselected NAND strings in the second sub-block, and
• apply a program voltage to the selected data word line.