Method of operating phase change memories, corresponding device and computer program product

A method of performing write operations in a Phase Change Memory device, the Phase Change Memory device comprising a first set of cells and a second set of cells configured to be set to a low logic level and to a high logic level, respectively, in response to write operations comprising reset write operations or set write operations;

• wherein the method comprises:
• performing, if the first set of cells contains at least one cell set at a high logic level, a reset write operation to set to a low logic level the at least one cell in the first set of cells by applying thereto at least one current reset pulse;
• performing, if the second set of cells contains at least one cell set at a low logic level, a set write operation to set to a high logic level the at least one cell in the second set of cells;
• verifying success or failure of the set write operation via at least one set verify operation to check if the at least one cell in the second set of cells is set to a high logic level in response to the set write operation;
• considering the set write operation:
• i) successful, in response to the at least one set verify operation indicating that the at least one cell in the second set of cells is set to a high logic level in response to the set write operation;
• and
• ii) failed, in response to the at least one set verify operation indicating that the at least one cell in the second set of cells is set to a low logic level in response to the set write operation;
• verifying success or failure of the reset write operation via at least one verify operation selected out of individual and looped reset write verify operations to check if the at least one cell in the first set of cells is set to a low logic level in response to the reset write operation;
• considering the reset write operation:
• i) successful, in response to any of the individual and looped reset write verify operations indicating that the at least one cell in the first set of cells is set to a low logic level in response to the reset write operation;
• and
• ii) failed, in response to all of the individual and looped reset write verify operations indicating that the at least one cell in the first set of cells is set to a high logic level in response to the reset write operation;
• and
• considering the write operation as failed in response to the reset write operation being considered as failed and/or to the set write operation being considered as failed.